Fabricating semiconductor devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to monitor and control one or more semiconductor layer processes. One of the characteristics being monitors and controlled is the overlay error. An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. The overlay error is typically determined with an overlay target having structures formed on one or more layers of a work piece (e.g., semiconductor wafer). If the two layers or patterns are properly formed, then the structure on one layer or pattern tends to be aligned relative to the structure on the other layer or pattern. If the two layers or patterns are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned relative to the structure on the other layer or pattern. Overlay error is the misalignment between any of the patterns used at different stages of the semiconductor fabrication processes.
When overlay errors are observed, an overlay measurement may be used to apply corrections and to keep overlay errors within desired limits. For example, overlay measurements may be fed into an analysis routine that calculates scanner corrections, referred to as “correctables”, as well as other statistics, which may be used by an operator in order to better align the lithography tool used in the process.
In typical fabrication operations, semiconductor manufacturing processes are run in batches called lots. A lot, or a wafer lot, is defined as a quantity of wafers which are processed together as a single group. Conventional overlay monitor and control techniques generally take a single set of scanner corrections and apply the same set for all wafers in the same lot. Such techniques need to be improved.